With increase in speed and integration of semiconductor chips (semiconductor elements), servers where semiconductor chips are installed use micro wires to couple the semiconductor chips and transmission speeds among the semiconductor chips have also been increasing. Three-dimensional packaging techniques are under development, which enable high-speed transmission by forming through silicon vias (TSVs) or the like in semiconductor chips, stacking the semiconductor chips, and coupling the semiconductor chips using minute bumps. According to such three-dimensional packaging techniques, since TSVs are formed in semiconductor chips, increase in cost for semiconductor chips and many problems related to processes are caused and the three-dimensional packaging techniques are limited to certain applications including memory. In addition, 2.5-dimensional packaging techniques are also under development, by which high-speed transmission is performed through a silicon interposer or the like arranged as an intermediate board between a semiconductor chip and a printed circuit board.
Also in the 2.5-dimensional packaging techniques, TSVs are formed in a silicon interposer and cost for such a silicon interposer increases. Although glass interposers are also under development so as to address the increase and reduce the cost, practical utilization has not been achieved, yet. For cost reduction, use of resin interposers (resin substrates) is under review.
FIGS. 11A to 11C are process diagrams that illustrate packaging techniques using a resin interposer. According to the packaging techniques using a resin interposer, as illustrated in FIG. 11A, solder bumps 110 are formed over a printed circuit board 101. After that, as illustrated in FIG. 11B, a resin interposer 102 is mounted over the printed circuit board 101 using a flip-chip bonder and as illustrated in FIG. 11C, semiconductor chips 103 are mounted over the resin interposer 102. On the semiconductor chips 103, for example, micro-bumps 131, which each have a height of 25 μm, a diameter Φ of 25 μm, and a pitch of 45 μm, are formed and the resin interposer 102 and the semiconductor chips 103 are joined to each other through the micro-bumps 131. Since the size of each micro-bump 131 is small, tolerance for warpage or waviness on a surface 121 of the resin interposer 102 is small. Accordingly, it is desirable for the surface 121 of the resin interposer 102 to be even.
A material of the resin interposer 102 is resin. Thus, when the resin interposer 102 is mounted over the printed circuit board 101, the rigidity of a member that supports the resin interposer 102 affects the resin interposer 102. As illustrated in FIGS. 11B and 11C, the solder bumps 110 and a solder resist 111 are formed between the printed circuit board 101 and the resin interposer 102, and the solder bumps 110 and the solder resist 111 support the resin interposer 102. As the shape of the resin interposer 102 follows the shape of the solder bumps 110 because of a difference in magnitude between the rigidity of each solder bump 110 and the rigidity of the solder resist 111, waviness is caused in the resin interposer 102. Accordingly, unevenness occurs on the surface 121 of the resin interposer 102. As the thickness of the resin interposer 102 decreases, the unevenness on the surface 121 of the resin interposer 102 increases. When for example, the thickness of the resin interposer 102 is 25 μm and the height of the solder bump 110 is 90 μm, the difference in level of the unevenness on the surface of the resin interposer 102 is 50 to 60 μm. Thus, it is difficult to mount the semiconductor chips 103 over the resin interposer 102 through the micro-bump 131 that each have a height of 25 μm for example.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2008-244104 and
[Document 2] Japanese Laid-open Patent Publication No. 2010-161184.